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MSTM-S3-IT3-19.44M Stratum 3 Timing Module
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Application
The Connor-Winfield MSTM-S3-IT3 Simplified Control Timing Module acts as a complete system clock module for Stratum 3 timing applications in accordance with GR1244, Issue 2 and GR-253, Issue 3. Connor Winfield's Stratum 3 timing modules helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design.
Features
* -40 to 85 Temp. Range * 5V Miniature Timing Module * Redundant 8kHz References * 40 sec., Filtered, Hold Over History * Operational Status Flags
Bulletin Page Revision Date Issued By
TM034 1 of 16 P01 04 DEC 02 MBatts
General Description
The Connor-Winfield Stratum 3 Simplified Control Timing Module acts as a complete system clock module for general Stratum 3 timing applications. Full external control input allows for selection and monitoring of any of four possible operating states: 1) Holdover, 2) External Reference #1, 3) External Reference #2, and 4) Free Run. Table #1 illustrates the control signal inputs and corresponding operational states. In the absence of External Control Inputs (A,B), the MSTM enters the Free Run mode and signals an External Alarm. The MSTM will enter other operating modes upon application of a proper control signal. Mode 1 operation (A=1, B=0) results in an output signal that is phase locked to the External Reference Input #1. Mode 2 operation (A=0, B=1) results in an output signal that is phase locked to External Reference Input #2. Holdover mode operation (A=1, B=1) results in an output signal at or near the frequency as determined by the latest (last) lockedsignal input values and the holdover performance of the MSTM. Free Run ModeFree Run mode operation (A=0, B=0) is a guaranteed output of 4.6 ppm of the nominal frequency. Alarm signals are generated at the Alarm Output during Holdover and Free Run operation. Alarm Signals are also generated by loss-of-lock, loss of Reference, and by a Tune-Limit indication from the PLL. A Tune-Limit alarm signal indicates that the OCXO tuning voltage is approaching within 10% the limits of its lock capability and that the External Reference Input may be erroneous. A high level indicates an alarm condition. Real-time indication of the operational mode is available at unique operating mode outputs on pins 1-4. Control loop 0.1 Hz filters effectively attenuate any reference jitter, smooth out phase transients, comply with wander transfer and jitter tolerances.
Functional Block Diagram
Figure 1
CNTL A CNTL B Mode Control Free Run Ref 1 Ref 2 Holdover PLL TVL Free Run Holdover
Alarm Out
Reference Select Ex Ref 1 Ex Ref 2 Phase Comparator LOL/LOR
SYNC_OUT DAC Filters Stratum 3 OCXO
DAC
Tuning Voltage Monitor
FIFO
PLL TVL
Function Control Table
Table 1
CNTL A 0 1 CNTL B 0 0 Operational Mode Free Run (Default Mode) External Reference #1 External Reference #2 Normal Tune Limit LOR + LOL Normal Tune Limit LOR + LOL Ref 1 0 1 1 1 0 0 0 0 Ref 2 0 0 0 0 1 1 1 0 Hold Over 0 0 0 0 0 0 0 1 Free Run 1 0 0 0 0 0 0 0 PLL_TVL 0 0 1 0 0 1 0 0 Alarm Out 1 0 1 1 0 1 1 1
0 1
1 1
Hold Over
Absolute Maximum Rating
Table 2
Symbol VCC VI Ts Parameter Power Supply Voltage Input Voltage Storage Temperature Minimum -0.5 -0.5 -55 Nominal Maximum 7.0 VCC + 0.5 100 Units Volts Volts deg. C Notes 1.0 1.0 1.0
Data Sheet #: TM034
Page 2 of 16
Rev: P01
Date: 12 / 04 / 02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended Operating Conditions
Table 3
Symbol Vcc VIH VIL tIN CIN VOH VOL tTRANS Parameter Power supply voltage High level input voltage - TTL Low level input voltage - TTL Input signal transition - TTL Input capacitance High level output voltage, IOH = -4.0mA, VCC = min. Low level output voltage, IOL = 12.0 mA, VCC = min. Clock out transition time 2.4 Minimum 4.75 2.0 0 Nominal 5.00 Maximum 5.25 VCC 0.8 250 15 5.25 0.4 Units Volts Volts Volts ns pF Volts Volts 2.0 Notes
4.0 30 -40 85
ns ns C
tPULSE TOP
8kHz input reference pulse width( positive or negative) Operating temperature
Specifications
Table 4
Parameter Frequency Range (SYNC_OUT) Supply Current Timing Reference Inputs Jitter, Wander and Phase Transient Tolerances Wander Generation Wander Transfer Jitter Generation Jitter Transfer Phase Transients Free Run Accuracy Hold Over Stability Inital Offset Temperature Drift Maximum Hold Over History Pull-in/ Hold-in Range Lock Time PLL_TVL Alarm Limit Specifications 19.44 MHz 250 mA typical, 400 mA during warm-up (Maximum) Dual 8 kHz references GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6 GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2 GR-1244-CORE 5.4 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1 GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3 4.6 ppm over TOP 0.37 ppm for initial 24 hrs 0.05 ppm 0.28 ppm 0.04 ppm 40 seconds 4.6 ppm minimum <100 sec. Extreme 10% ranges of Pull-in/Hold-in Range 5.0 4.0 3.0 Notes
NOTES: 1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage to the device. Operation beyond Recommended Conditions is not implied. 2.0: 3.0 Logic is 3.3V CMOS GR-1244-CORE 3.2.1
4.0: 5.0:
Hold Over stability is the cumulative fractional frequency offset as described by GR-1244-CORE, 5.2 Pull-in Range is the maximum frequency deviation from nominal clock rate on the reference inputs to the timing module that can be overcome to pull into synchronization with the reference
Data Sheet #: TM034
(c) Copyright 2002 The Connor-Winfield Corp.
Page 3 of 16
Rev: P01
Date: 12 / 04 / 02
All Rights Reserved Specifications subject to change without notice
Pin Description
Table 5 Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Connection
HOLD OVER REF 1 REF 2 FREE RUN GND ALARM _OUT CNTL A CNTL B PLL_TVL GND SYNC_OUT GND N/C GND EX_REF_2 GND EX_REF_1 VCC
Description
Indicator output. High output when Hold Over mode is selected by control pins. Indicator output. High output when Ref 1 mode is selected by control pins. Indicator output. High output when Ref 2 mode is selected by control pins. Indicator output. High output when Free Run mode is selected by control pins. Ground Alarm output. High output if module is in Free Run, or Hold Over, or LOR, or LOL, or PLL_TVL mode. Mode control input Mode control input Tuning Voltage Limit alarm output. High output when Sync_Out is near the extreme 10% ranges of the Pull-in/Hold-in range. Ground Primary timing output signal. Signal is sychronized to reference. Ground Do not connect. It may affect the module adversely if a signal is apllied. Ground External Input Reference #2 Ground External Input Reference #1 +5V dc supply
Typical Application
Figure 2
BITS System Signal
Input Select
#1 MUX Y #N S
Timing Card #1
CW's STM/MSTM module
Line Card #1
CW's SCG 2500/4500
Clockout
RCV
#1 MUX Y #N S
Timing Card #2
CW's STM/MSTM module
Line Card #N
CW's SCG 2500/4500
Clockout
RCV
System Select
Data Sheet #: TM034
Page 4 of 16
Rev: P01
Date: 12 / 04 / 02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Module Test Set-up
Figure 3
Vcc
Stratum 1 Reference
1 - Hold Over 2 - Ref 1 3 - Ref 2 4 - Free Run 5 - Gnd Vcc 6 - Alarm Out 7 - Cntl A 8 - Cntl B 9 - PLL_TVL
5 Vdc - 18 Ext. Ref 1 - 17 Gnd - 16 Ext. Ref 2 - 15 Gnd - 14 Oscilloscope N/C - 13 Gnd - 12 Frequency Counter Sync_Out - 11 Gnd - 10 Probe Probe 8 kHz Stratum 1 Traceable Signal
10 MHz
Top View
Typical System Test Set-up
Figure 4
This device supplies system time information. It can be thought of as supplying "absolute time" reference information GPS or LORAN Timing Source
S a m p le M T IE D a t a fo r S T M -S 3 /M S T M - S 3
1 .0 E -6
10 MHz
M T IE (s
Possible Choices Include Stanford Research Model: FS700 Truetime Model XXX
T ypic al res po n s e - 3000 se c o nd te st - Jitte r a pplie d (2 U I @ 10 H z) re f da te A P R 22 1998 k dh
1 0 0 .0 E -9
1 0 .0 E -9
M TIE 1 2 4 4 - 5 .2 M a s k ( A ) 1 2 4 4 - 5 .2 M a s k ( B ) 1 2 4 4 - 5 .6 M a s k G R2 5 3 - 5 .4 .4 .3 . 2
1 .0 E -9 1 0 0 .0 E -3 1 .0E +0 10 .0E +0 1 0 0 .0 E +0 1.0 E+ 3 1 0 .0 E +3
O bs e r va tion Tim e (s )
C o pyright 1998 C o n n o r-W in fie ld a ll righ ts re se rve d
Target System Under Test
External Reference Input
Arbitrary Waveform Generator
DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz clock RZ with noise modulation
Clock or BITS logic level clock input (TTL, CMOS, etc.)
Standards Compliance Documents MTIE, TDEV, Wander Transfer, and Wander Generation Plots OC-12 Line Card OC-48 Line Card OC-3 Line Card DS-1 Line Card Timing Card Timing Card Line Card
S a m p le W a n d e r G e n e r a t io n (T D E V ) f o r S T M /M S T M - S 3
1.0 E- 6
Noise Modulation Input
T ypica l re s po n s e - 3000 s ec o nd te st - Jitter a pplie d ( 2 UI @ 10 H z) re f da te A P R 22 1998 k dh
10 MHz
1 0 0.0 E- 9
. . . . ...
1 0.0 E- 9
TD E V (s e c
T DEV
1.0 E- 9
G R1 2 4 4 - F ig 5 . 1 G R1 2 4 4 - F ig 5 - 3
External Reference Input
Arbitrary Waveform Generator [Noise Source]
1 0 0 .0 E -1 2 10 .0E -3
10 0 .0 E -3
1 .0 E +0
1 0.0 E+0
1 00 .0E +0
1 .0 E +3
In te g r a t io n T im e ( s e c )
C o pyrigh t 1998 C o n no r-W in fie ld alll righ ts res e rv e d
DS1 rate [1.544 MHz] BITS Bipolar DS-1, OC-3, OC-12 electrical or optical signals 10 MHz Tektronix SJ300E
10 MHz
Time-stamped ensemble based on absolute time reference (10MHz input) Phase Error data output
External Reference Input
HP53310A Modulation Analyzer / Time Interval Analyzer
Wander Analyzer data (IEEE-488)
External Reference Input
TEKTRONIX SJ300E
IEEE-488 Controller Platform for software HP 53305A Phase Analyzer HP E1748A Sync Measurement Tektronix Wander Analyzer
Data Sheet #: TM034
(c) Copyright 2002 The Connor-Winfield Corp.
Page 5 of 16
Rev: P01
Date: 12 / 04 / 02
All Rights Reserved Specifications subject to change without notice
MSTM-S3-IT3 Typical Current Draw
Figure 5
0.4 0.38 0.36 0.34 Current (Amps) 0.32 0.3 0.28 0.26 0.24 0.22 0.2 0 10 20 30 Time (sec) 40 50 60
MSTM-S3-IT3 Typical Phase Noise Plot
Figure 6
0 -20 -40 -60 dBc/Hz -80 -100 -120 -140 -160 -180 10.0E+0
100.0E+0
1.0E+3
10.0E+3 Hz
100.0E+3
1.0E+6
10.0E+6
Data Sheet #: TM034
Page 6 of 16
Rev: P01
Date: 12 / 04 / 02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
MSTM-S3-IT3 Typical Phase Gain
Figure 7
10.00 0.00 -10.00 -20.00 -30.00 Phase Gain (dB) -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 -110.00 0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
Reference Modulation Frequency (Hz)
MSTM-S3-IT3 Typical Hold Over Stability over Temperature
Figure 8
250
200 Frequency Offset (ppb)
150
100
50
0 0 10 20 30 40 50 60 70 Temperature (C)
Data Sheet #: TM034
(c) Copyright 2002 The Connor-Winfield Corp.
Page 7 of 16
Rev: P01
Date: 12 / 04 / 02
All Rights Reserved Specifications subject to change without notice
Typical Wander Generation MTIE
Figure 9
1000
GR1244, Fig 5.2 (A) GR1244, Fig 5.2 (B) GR253-5.4.4.3.2, Fig 5.17 Jittered Reference Pristine Reference Temperature Stressed Reference 100
MTIE (ns)
10 1 0.1 1 10 100 1000 10000 100000 1000000
Observation Time (sec.)
Typical Wander Generation TDEV
Figure 10
100
GR1244, Fig 5.1 Jitte re d Re fe re nce Pristine Re fe re nce Te m pe ra ture S tre sse d Re fe re nce
10
TDEV (ns)
1
0.1
0.01 0.1 1
Integration Time (sec.)
10
100
1000
10000
Data Sheet #: TM034
Page 8 of 16
Rev: P01
Date: 12 / 04 / 02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Calibrated Wander Transfer TDEV
Figure 11
10000
1000
TDEV (ns)
100
TDEV (ns) GR1244, Fig 5.3
10
1 0.01
0.1
1
10
100
1000
10000
Integration Time (Sec.)
Typical Reference Switch MTIE
Figure 12
10000 GR1244, Fig 5-7, Stratum 2/3E GR1244, Fig 5-7, Stratum 3/4E MTIE (ns) 1000
MTIE (ns)
100
10
1 0.001
0.01
0.1
1 Observation Time (sec)
10
100
1000
Data Sheet #: TM034
(c) Copyright 2002 The Connor-Winfield Corp.
Page 9 of 16
Rev: P01
Date: 12 / 04 / 02
All Rights Reserved Specifications subject to change without notice
Typical Entry Into Hold Over MTIE
Figure 13
10000
1000
MTIE (ns)
100
10
G R -1 2 4 4 O b je c tive , F i g . 5 -8 G R -1 2 4 4 R e q uire m e nt, F i g . 5 -8 G R -2 5 3 , F ig . 5 -1 9 , R e q uire m e nt T yp ic a l M T IE
1 0 .0 0 1
0 .0 1
0 .1
1 O b s e rv a tio n T im e (s e c o n d s )
10
100
1000
Typical Return from Hold Over MTIE
Figure 14
10000
1000
MTIE (ns)
100
10 G R -1 2 4 4 R e q u ire m e n t , F ig . 5 -7 M TIE (n s ) Ty p ic a l M TIE
1 0.001
0.01
0.1 O b se r v a ti o n T i m e (se c . )
1
10
100
Data Sheet #: TM034
Page 10 of 16
Rev: P01
Date: 12 / 04 / 02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical 1us Phase Transient TIE
Figure 15
1200
1000
800
TIE (ns)
600
400
200
0
-200 0 1 2 3 4 5 Time (sec) 6 7 8 9 10
Typical Phase Transient MTIE
Figure 16
10000
1000
MTIE (ns)
G R -2 5 3 , F i g . 5 -1 9 , R e q u i r e m e n t M T I E (n s)
100
10
1 0 .0 1 0 .1 1 10 100 1000 O b s e rv a tio n T im e (s e c )
Data Sheet #: TM034
(c) Copyright 2002 The Connor-Winfield Corp.
Page 11 of 16
Rev: P01
Date: 12 / 04 / 02
All Rights Reserved Specifications subject to change without notice
MSTM-S3-IT3 Mode Indicator Delay
Figure 17
Change in Operational Mode
Operational Mode Indicator tm
2 msec < tm < 4.125 msec
Tuning Voltage Limit Alarm Timing Diagram
Figure 18
TVL Limit High Frequency Sync_Out
(Nominal Frequency)
TVL Limit Low Frequency TVL Alarm & Alarm Out t 0 < t < 2.125 msec *The DAC is updated only when the output changes level. The maximum update rate is 8 kHz
Data Sheet #: TM034
Page 12 of 16
Rev: P01
Date: 12 / 04 / 02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Reference Timing Diagram
Figure 19
External Reference Input
Alarm tAon tAoff
2 msec < tAon < 6.125 msec 0 msec < tAoff < 2.125 msec
Solder Clearance
Figure 20
.020" MAX.
.020"
.030" PIN LAND
ALL SOLDER AND/OR WIRE TAGS SHALL NOT EXTEND MORE THAN .020" BELOW PC BOARD BOTTOM SURFACE
Data Sheet #: TM034
(c) Copyright 2002 The Connor-Winfield Corp.
Page 13 of 16
Rev: P01
Date: 12 / 04 / 02
All Rights Reserved Specifications subject to change without notice
MECHANICAL OUTLINE:
The mechanical outline of the MSTM-S3-IT3 is shown in Figure 21. The board space required is 2" x 2". The pins are .040" in diameter and are .150" in length. The unit is spaced off the PCB by .030" shoulders on the pins. Due to the height of the device it is recommended to have heat sensitive devices away where the air flow might not be blocked.
GROUND AND POWER SUPPLY LINES:
Power specifications will vary depending primarily on the temperature range. At wider temperature ranges starting at 0 to 70 deg. C., an ovenized oscillator, OCXO, will be incorporated. The turn-on current for an OCXO requires a peak current of about .4A for about a minute. The steady state current will the vary from 50-150 mA depending on the temperature. It is suggested to plan for the peak current in the power and ground traces pin 18 and pin 5. The other four ground pins 10, 12, 14, and 16 are intended for signal grounds.
PAD ARRAY AND PAD SPACING:
The pins are arranged in a dual-in-line configuration as shown in Figure 21. There is .2" space between the pins in-line and each line is separated by 1.6". See Figures 21 & 22 and Table 6.
POWER SUPPLY REGULATION:
Good power supply regulation is recommended for the MSTM-S3-IT3 The internal oscillators are regulated to operate from 4.75 - 5.25 volts. Large jumps within this range may still produce varying degrees of wander. If the host system is subject to large voltage jumps due to hot-swapping and the like, it is suggested that there be some form of external regulation such as a DC/DC converter.
PAD CONSTRUCTION:
The recommended pad construction is shown in Figure 23. For the pin diameter of .040" a hole diameter of .055" is suggested for ease of insertion and rework. A pad diameter of .150" is also suggested for support. This leaves a spacing of .050" between the pads which is sufficient for most signal lines to pass through.
SOLDERING RECOMMENDATIONS:
Due to the sensitive nature of this part, hand soldering or wave soldering of the pins is recommended after reflow processes.
SOLDER MASK:
A solder mask is recommended to cover most the top pad to avoid excessive solder underneath the shoulder of the pin to avoid rework damage. See Table 6 and Figure 23.
WASHING RECOMMENDATIONS:
The MSTM-S3-IT3 is not in a hermetic enclosure. It is recommended that the leads be hand cleaned after soldering. Do not completely immerse the module.
VIA KEEP OUT AREA:
It is recommended that there be no vias or feed throughs underneath the main body of the module between the pins. It is suggested that the traces in this area be kept to a minimum and protected by a layer of solder mask. See Figure 22.
MODULE BAKEOUT:
Do not bakeout the MSTM-S3-IT3
Data Sheet #: TM034
Page 14 of 16
Rev: P01
Date: 12 / 04 / 02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Package Dimensions
Figure 21
Characteristic Measurements
Table 6
Characteristic Item
Pad to Pad Spacing Solder pad top O.D. Solder pad top I.D. Solder pad bottom O.D. Solder pad bottom I.D. Solder mask top dia. Solder mask bottom dia. Pin row to row spacing
Measurement (inches)
0.200 0.150 0.055 0.150 0.055 0.070 0.155 1.600
Recommended Footprint Dimensions
Figure 22
Side Assembly View
Figure 23
TOP SIDE SOLDER RESIST (OVER PAD)
PCB SIDE VIEW
BOTTOM SIDE SOLDER RESIST (UP TO PAD)
Data Sheet #: TM034
(c) Copyright 2002 The Connor-Winfield Corp.
Page 15 of 16
Rev: P01
Date: 12 / 04 / 02
All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Revision
P00 P01
Revision Date
12/07/01 12/04/02
Note
Final Release Increased upper temp. range to 85 C

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